The present invention relates generally to static random access memory (SRAM) cell, and, more particularly, to SRAM cells that can operate under ultra-low voltage.
Semiconductor memory devices include, for example, static random access memory, or SRAM, and dynamic random access memory, or DRAM. DRAM memory cell has only one transistor and one capacitor, so it provides a high degree of integration. But DRAM requires constant refreshing, its power consumption and slow speed limit its use mainly for computer main memories. SRAM cell, on the other hand, is bi-stable, meaning it can maintain its state indefinitely as long as an adequate power is supplied. SRAM can operate at a higher speed and lower power dissipation, so computer cache memories use exclusively SRAMs. Other applications include embedded memories and networking equipment memories.
One well-known conventional structure of a SRAM cell is a six transistor (6T) cell that comprises six metal-oxide-semiconductor (MOS) transistors. Briefly, a 6T SRAM cell 100, as shown in FIG. 1, comprises two identical cross-coupled inverters 102 and 104 that form a latch circuit, i.e., one inverter's output connected to the other inverter's input. The latch circuit is connected between a power and a ground. Each inverter 102 or 104 comprises a NMOS pull-down transistor 115 or 125 and a PMOS pull-up transistor 110 or 120. The inverter's outputs serve as two storage nodes C and D, when one is pulled to low voltage, the other is pulled to high voltage. A complementary bit-line pair 150 and 155 is coupled to the pair of storage nodes C and D via a pair of pass-gate transistors 130 and 135, respectively. The gates of the pass-gate transistors 130 and 135 are commonly connected to a word-line 140. When the word-line voltage is switched to a system high voltage, or Vcc, the pass-gate transistors 130 and 135 are turned on to allow the storage nodes C and D to be accessible by the bit-line pair 150 and 155, respectively. When the word-line voltage is switched to a system low voltage, or Vss, the pass-gate transistors 130 and 135 are turned off and the storage nodes C and D are essentially isolated from the bit lines, although some leakage can occur. Nevertheless, as long as Vcc is maintained above a threshold, the state of the storage nodes C and D is maintained indefinitely.
However, the traditional 6T SRAM cell 100 faces many challenges as processes migrate to deep submicron technologies. One of the challenges is adapting very low operating voltages to transistor's small sizes. The low operating voltage causes read operation instability as the transistors' threshold voltages are too large as compared with the operating voltage, hence leaving little switching margins. Another challenge is that during a read operation, the storage nodes C and D are directly coupled to the bit-lines 150 and 155, respectively, and thus are susceptible to charge sharing effects which also cause read operation instability especially when there is a large number of cells in the bit-lines 150 and 155.
As such, what is desired is a SRAM cell that has stable operations even in low operating voltages and large cell arrays.